Three-dimensional semiconductor memory devices including a vertical channel

ABSTRACT

Semiconductor memory devices and methods of forming the semiconductor devices may be provided. The semiconductor memory devices may include a channel portion of an active pillar that may be formed of a semiconductor material having a charge mobility greater than a charge mobility of silicon. The semiconductor devices may also include a non-channel portion of the active pillar including a semiconductor material having a high silicon content.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35U.S.C. §119 to Korean Patent Application No. 10-2014-0047447, filed onApr. 21, 2014, in the Korean Intellectual Property Office, thedisclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The inventive concept generally relates to the field of electronics and,more particularly, to semiconductor memory devices.

A three-dimensional integrated circuit (3D-IC) memory technique has beendeveloped to increase memory capacity of a semiconductor memory device.The 3D-IC memory technique includes a variety of methods for arrangingmemory cells three-dimensionally. As well as the 3D-IC memory technique,a patterning technique for fine patterns and a multi-level cell (MLC)technique may be used to increase the memory capacity of thesemiconductor memory device. However, the patterning technique for thefine patterns may be very expensive, and the MLC technique may not besuitable to increase the number of bits per a unit cell. Thus, the 3D-ICmemory technique may be important to increase the memory capacity. Inaddition, if the patterning technique for the fine patterns and the MLCtechnique are combined with the 3D-IC memory technique, the memorycapacity may more increase. Thus, the patterning technique for the finepatterns and the MLC technique may be developed independently of the3D-IC memory technique.

SUMMARY

Some embodiments of the inventive concept may provide semiconductormemory devices capable of improve a cell current.

A semiconductor memory device may include an active pillar protrudingfrom a substrate, a gate electrode adjacent to a sidewall of the activepillar, and a gate dielectric layer disposed between the active pillarand the gate electrode. The active pillar may include a first portionbeing in contact with the gate dielectric layer, and a second portionspaced apart from the gate dielectric layer. The first portion mayinclude a semiconductor material of which charge mobility is greaterthan that of silicon.

In some embodiments, a silicon content of the second portion may behigher than that of the first portion.

In some embodiments, the first portion of the active pillar may includea first semiconductor layer, and the second portion of the active pillarmay include a second semiconductor layer. The first semiconductor layermay include at least one of germanium (Ge), silicon-germanium (SiGe),gallium-arsenic (GaAs), indium-gallium-arsenic (InGaAs), and/oraluminum-gallium-arsenic (AlGaAs), and a silicon content of the secondsemiconductor layer may be higher than that of the first semiconductorlayer.

In some embodiments, the active pillar may further include a thirdsemiconductor layer covering a sidewall of the second semiconductorlayer. The third semiconductor layer may include a silicon layer.

In some embodiments, the active pillar may include a single-layeredsilicon-germanium layer, and a germanium content of the first portionmay be higher than that of the second portion.

In some embodiments, the semiconductor memory device may further includeintergate insulating layers adjacent to the sidewall of the activepillar and disposed on and under the gate electrode. The gate dielectriclayer may include a tunnel dielectric layer, a charge storage layer, anda blocking dielectric layer which are sequentially stacked on thesidewall of the active pillar, and the tunnel dielectric layer may beformed of a thermal oxide layer and may cover only a portion of thesidewall of the active pillar. The charge storage layer and the blockingdielectric layer may be disposed between the gate electrode and theactive pillar and between the gate electrode and the intergateinsulating layers.

In some embodiments, the gate dielectric layer may include a tunneldielectric layer, a charge storage layer, and a blocking dielectriclayer which are sequentially stacked on the sidewall of the activepillar.

In some embodiments, the first portion may have a thickness of about 50Å or more.

In some embodiments, the active pillar may have an amorphous structure,a single-crystalline structure, or a poly-crystalline structure.

In some embodiments, the semiconductor memory device may further includeintergate insulating layers adjacent to the sidewall of the activepillar and disposed on and under the gate electrode. The gate dielectriclayer may extend to be disposed between the active pillar and theintergate insulating layers.

In some embodiments, the first portion of the active pillar may includean ‘L’-shaped semiconductor layer.

A semiconductor memory device may include intergate insulating layersand gate electrodes alternately stacked on a substrate, an active pillarpenetrating the intergate insulating layers and the gate electrodes soas to be connected to the substrate, and a first gate dielectric layercovering a sidewall of the active pillar. The active pillar may includea first portion being in contact with the first gate dielectric layer,and a second portion spaced apart from the first gate dielectric layer.The first portion may include a semiconductor material of which chargemobility is greater than that of silicon, and the second portion mayinclude a semiconductor material having a high silicon content and maybe connected to the substrate.

In some embodiments, the first gate dielectric layer may include atunnel dielectric layer, a charge storage layer, and a blockingdielectric layer which are sequentially stacked on a sidewall of thefirst portion of the active pillar.

In some embodiments, the first portion of the active pillar may includea first semiconductor layer, and the second portion of the active pillarmay include a second semiconductor layer. The first semiconductor layermay include the semiconductor material of which the charge mobility isgreater than that of silicon. A bottom surface of the firstsemiconductor layer may be spaced apart from the substrate. The secondsemiconductor layer may include a silicon layer and may be connected tothe substrate.

In some embodiments, the semiconductor memory device may further includea second gate dielectric layer disposed between the gate electrodes andthe intergate insulating layers and between the first gate dielectriclayer and the gate electrodes. A dielectric constant of the second gatedielectric layer may be higher than that of a silicon oxide layer.

In some embodiments, the first semiconductor layer may include at leastone of germanium (Ge), silicon-germanium (SiGe), gallium-arsenic (GaAs),indium-gallium-arsenic (InGaAs), and/or aluminum-gallium-arsenic(AlGaAs).

In some embodiments, the first semiconductor layer of the active pillarmay have a poly-crystalline structure.

A semiconductor memory device may include an active pillar protrudingfrom a substrate, gate electrodes surrounding the active pillar andsequentially stacked on the substrate, and a gate dielectric layerdisposed between the active pillar and the gate electrodes. The activepillar may include a first portion being in contact with the gatedielectric layer, and a second portion spaced apart from the gatedielectric layer. The first portion may include a first semiconductorlayer of which charge mobility is greater that of silicon. The firstsemiconductor layer may have a ‘L’-shape. The second portion may includea second semiconductor layer having a silicon.

In some embodiments, the first semiconductor layer may include at leastone of germanium (Ge), silicon-germanium (SiGe), gallium-arsenic (GaAs),indium-gallium-arsenic (InGaAs), and/or aluminum-gallium-arsenic(AlGaAs), and the second semiconductor layer may include a siliconlayer.

In some embodiments, the first portion of the active pillar may includea first silicon-germanium (SiGe) layer, and the second portion of theactive pillar may include a second silicon-germanium (SiGe) layer. Asilicon content of the first silicon-germanium (SiGe) layer may be lowerthan a silicon content of the second silicon-germanium (SiGe) layer.

In yet another aspect, a method of fabricating a semiconductor memorydevice may include alternately and repeatedly stacking intergateinsulating layers and sacrificial layers on a substrate, patterning theintergate insulating layers and the sacrificial layers to form an activehole exposing the substrate, forming an active pillar in the activehole, the active pillar connected to the substrate, removing thesacrificial layers to form empty regions exposing a sidewall of theactive pillar, forming a first gate dielectric layer on the exposedsidewall of the active pillar, and forming gate electrodes in the emptyregions. The active pillar may include a first portion being in contactwith the first gate dielectric layer; and a second portion spaced apartfrom the gate dielectric layer. The first portion may include asemiconductor material of which charge mobility is greater than that ofsilicon.

In some embodiments, the active pillar may be formed of asilicon-germanium layer. In this case, forming the first gate insulatinglayer may include oxidizing the exposed sidewall of the active pillarand causing a gradient of a germanium content according to a position inthe active pillar at the same time.

In some embodiments, forming the active pillar may include sequentiallyforming a first semiconductor layer and a second semiconductor layer ona sidewall and a bottom surface of the active hole.

In some embodiments, the method may further include forming a secondgate dielectric layer covering the sidewall and the bottom surface ofthe active hole before forming the first semiconductor layer. In thiscase, forming the active pillar may include anisotropically etching thesecond semiconductor layer, the first semiconductor layer, and thesecond gate dielectric layer to leave portions of the second and firstsemiconductor layers and the second gate dielectric layer on thesidewall of the active hole and to expose the substrate of the bottomsurface of the active hole, and forming a third semiconductor layercovering a sidewall of the second semiconductor layer and the bottomsurface of the active hole.

In some embodiments, the first semiconductor layer may include amaterial of which the charge mobility is greater than that of silicon,and the second semiconductor layer may include a silicon layer.

In some embodiments, forming the active pillar may further includeperforming a solid phase crystallization process to have apoly-crystalline structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a semiconductor memory device accordingto example embodiments of the inventive concept.

FIG. 2 is a plan view illustrating a semiconductor memory deviceaccording to example embodiments of the inventive concept.

FIG. 3 is a cross-sectional view taken along the line A-A′ of FIG. 2 toillustrate a semiconductor memory device according to some embodimentsof the inventive concept.

FIGS. 4 to 9 are cross-sectional views illustrating a method offabricating the semiconductor memory device of FIG. 3.

FIG. 10 is a cross-sectional view taken along a line A-A′ of FIG. 2 toillustrate a semiconductor memory device according to some embodimentsof the inventive concept.

FIG. 11 is a cross-sectional view illustrating a method of fabricatingthe semiconductor memory device of FIG. 10.

FIG. 12 is a cross-sectional view taken along a line A-A′ of FIG. 2 toillustrate a semiconductor memory device according to some embodimentsof the inventive concept.

FIG. 13 is an enlarged view of the portion B1 of FIG. 12 according tosome embodiments of the inventive concept.

FIG. 14 is a graph illustrating a germanium content according to aposition in an active pillar of FIG. 13.

FIG. 15 is a cross-sectional view illustrating a method of fabricatingthe semiconductor memory device of FIG. 12.

FIG. 16 is a schematic block diagram illustrating an electronic systemincluding a semiconductor device according to some embodiments of theinventive concept.

FIG. 17 is a schematic block diagram illustrating a data storage deviceincluding a semiconductor memory device according to some embodiments ofthe inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The inventive concept will now be described more fully hereinafter withreference to the accompanying drawings, in which some embodiments of theinventive concept are shown. The advantages and features of theinventive concept and methods of achieving them will be apparent fromthe following embodiments that will be described in more detail withreference to the accompanying drawings. It should be noted, however,that the inventive concept is not limited to the following embodiments,and may be implemented in various forms. Accordingly, the embodimentsare provided only to disclose the inventive concept and let thoseskilled in the art know the category of the inventive concept. In thedrawings, embodiments of the inventive concept are not limited to thespecific examples provided herein and are exaggerated for clarity.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to limit the invention. As usedherein, the singular terms “a,” “an” and “the” are intended to includethe plural forms as well, unless the context clearly indicatesotherwise. As used herein, the term “and/or” includes any and allcombinations of one or more of the associated listed items. It will beunderstood that when an element is referred to as being “connected” or“coupled” to another element, it may be directly connected or coupled tothe other element or intervening elements may be present.

Similarly, it will be understood that when an element such as a layer,region or substrate is referred to as being “on” another element, it canbe directly on the other element or intervening elements may be present.In contrast, the term “directly” means that there are no interveningelements. It will be further understood that the terms “comprises”,“comprising,”, “includes” and/or “including”, when used herein, specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Additionally, the embodiment in the detailed description will bedescribed with sectional views as ideal views of the inventive concept.Accordingly, shapes of the views may be modified according tomanufacturing techniques and/or allowable errors. Therefore, theembodiments of the inventive concept are not limited to the specificshape illustrated in the views, but may include other shapes that may becreated according to manufacturing processes. Areas exemplified in thedrawings have general properties, and are used to illustrate specificshapes of elements. Thus, this should not be construed as limited to thescope of the inventive concept.

It will be also understood that although the terms first, second, thirdetc. may be used herein to describe various elements, these elementsshould not be limited by these terms. These terms are only used todistinguish one element from another element. Thus, a first element insome embodiments could be termed a second element in other embodimentswithout departing from the teachings of the present invention. Someembodiments of aspects of the present inventive concept explained andillustrated herein include their complementary counterparts. The samereference numerals or the same reference designators denote the sameelements throughout the specification.

Moreover, some embodiments are described herein with reference tocross-sectional illustrations and/or plan illustrations that areidealized illustrations. Accordingly, variations from the shapes of theillustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, embodiments should not beconstrued as limited to the shapes of regions illustrated herein but areto include deviations in shapes that result, for example, frommanufacturing. For example, an etching region illustrated as a rectanglewill, typically, have rounded or curved features. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the actual shape of a region of a device andare not intended to limit the scope of example embodiments.

As appreciated by the present inventive entity, devices and methods offorming devices according to various embodiments described herein may beembodied in microelectronic devices such as integrated circuits, whereina plurality of devices according to various embodiments described hereinare integrated in the same microelectronic device. Accordingly, thecross-sectional view(s) illustrated herein may be replicated in twodifferent directions, which need not be orthogonal, in themicroelectronic device. Thus, a plan view of the microelectronic devicethat embodies devices according to various embodiments described hereinmay include a plurality of the devices in an array and/or in atwo-dimensional pattern that is based on the functionality of themicroelectronic device.

The devices according to various embodiments described herein may beinterspersed among other devices depending on the functionality of themicroelectronic device. Moreover, microelectronic devices according tovarious embodiments described herein may be replicated in a thirddirection that may be orthogonal to the two different directions, toprovide three-dimensional integrated circuits.

Accordingly, the cross-sectional view(s) illustrated herein providesupport for a plurality of devices according to various embodimentsdescribed herein that extend along two different directions in a planview and/or in three different directions in a perspective view. Forexample, when a single active region is illustrated in a cross-sectionalview of a device/structure, the device/structure may include a pluralityof active regions and transistor structures (or memory cell structures,gate structures, etc., as appropriate to the case) thereon, as would beillustrated by a plan view of the device/structure.

Hereinafter, some embodiments of the inventive concept will be describedin detail. A memory device according to some embodiments of theinventive concept is a non-volatile memory device and has a structure ofa three-dimensional (3D) semiconductor memory device.

FIG. 1 is a circuit diagram of a semiconductor memory device accordingto example embodiments of the inventive concept. FIG. 2 is a plan viewillustrating a semiconductor memory device according to exampleembodiments of the inventive concept. FIG. 3 is a cross-sectional viewtaken along the line A-A′ of FIG. 2 to illustrate a semiconductor memorydevice according to some embodiments of the inventive concept.

Referring to FIGS. 1 to 3, a vertical type semiconductor memory deviceaccording to some embodiments of the inventive concept may include acommon source line CSL, a plurality of bit lines BL0, BL1, and BL2, anda plurality of cell strings CSTR disposed between the common source lineCSL and the bit lines BL0, BL1, and BL2.

The common source line CSL may be a dopant injection region that isformed in a substrate 1. The substrate 1 may be a semiconductorsubstrate or may include the semiconductor substrate and an epitaxialsemiconductor layer formed on the semiconductor substrate. The bit linesBL0, BL1, and BL2 may be conductive lines that are spaced apart from thesubstrate 1 and are disposed over the substrate 1. The bit lines BL0,BL1, and BL2 may be two-dimensionally arranged, and a plurality of cellstrings CSTR may be connected in parallel to each of the bit lines BL0,BL1, and BL2. The cell strings CSTR may be two-dimensionally arranged onthe substrate 1.

Each of the cell strings CSTR may include a lower selection transistorLST connected to the common source line CSL, an upper selectiontransistor UST connected to the bit line BL, and a plurality of memorycell transistors MCT disposed between the lower and upper selectiontransistors LST and UST. The lower selection transistor LST, the memorycell transistors MCT, and the upper selection transistor UST may beconnected in series to each other in a direction vertical (e.g.,perpendicular) to a top surface of the substrate 1. A lower selectionline LSL, a plurality of word lines WL0 to WL3, and an upper selectionline USL, which are disposed between the common source line CSL and thebit lines BL0, BL1, and BL2, may be used as gate electrodes of the lowerselection transistor LST, the memory cell transistors MCT, and the upperselection transistor UST, respectively. The common source line CSL, thelower selection line LSL, the word lines WL0 to WL3, and the upperselection line USL may extend in a first direction X. The bit lines BL0,BL1, and BL2 may extend in a second direction Y intersecting the firstdirection X. A third direction Z may be substantially perpendicular tothe first direction X and the second direction Y.

Distances of the gate electrodes of the lower selection transistors LSTfrom the substrate 1 may be substantially equal to each other. Gateelectrodes of the lower selection transistors LST may be at anequipotential state because they are connected in common to the lowerselection line LSL. Likewise, gate electrodes of the memory celltransistors MCT disposed at a substantially same distance from thecommon source line CSL may be connected in common to one of the wordlines WL0 to WL3, so they may be at an equipotential state. Since onecell string CSTR includes the plurality of memory cell transistors MCTrespectively disposed at different distances from the common source lineCSL, the plurality of word lines WL0 to WL3 may be sequentially stackedbetween the common source line CSL and the bit lines BL0, BL1, and BL2.

Each of the cell strings CSTR may include an active pillar AP thatvertically extends from the substrate 1. The active pillar AP may beconnected to the bit line BL. The active pillar AP may be formed topenetrate the upper selection line USL, the word lines WL0 to WL3, andthe lower selection line LSL.

A first gate dielectric layer 11 may be disposed between the activepillar AP and the lines USL, WL0 to WL3, and LSL. According to someembodiments, the first gate dielectric layer 11 may include a tunneldielectric layer, a charge storage layer, and a blocking dielectriclayer. In some embodiments, the charge storage layer may not existbetween the lower selection line LSL and the active pillar AP and/orbetween the upper selection line USL and the active pillar AP. A secondgate dielectric layer 22 may be disposed between the first gatedielectric layer 11 and the lines USL, WL0 to WL3, and LSL. The secondgate dielectric layer 22 may include a blocking dielectric layer. Thesecond gate dielectric layer 22 may include a high-k dielectric layer ofwhich a dielectric constant is higher than that of a silicon oxidelayer. A drain region D may be disposed in a top end portion of theactive pillar AP.

The lower and upper selection transistors LST and UST and the memorycell transistors MCT may be metal-oxide-semiconductor (MOS) field effecttransistors using the active pillar AP as channel regions. The activepillar AP may have a cup shape. A first filling insulation pattern 17may be disposed in the active pillar AP. In some embodiments, the upperselection line USL may include two upper selection lines USL that aresequentially stacked, and the lower selection line LSL may include twolower selection lines LSL that are sequentially stacked.

A buffer oxide layer 3 may be disposed on the substrate 1. Intergateinsulating layers 7 may be disposed on a top one of the upper selectionlines USL, between the upper selection lines USL, between a bottom oneof the upper selection lines USL and the word line WL3, between the wordlines WL0 to WL3, between the word line WL0 and a top one of the lowerselection lines LSL, and between the lower selection lines LSL. Thelower selection lines LSL, the word lines WL0 to WL3, and the upperselection lines USL which are sequentially stacked may constitute astack structure. A second filling insulation pattern 20 may be disposedbetween the stack structures that are laterally adjacent to each other.The common source line CSL may be disposed in the substrate 1 under thesecond filling insulation pattern 20. The second filling insulationpattern 20 may be disposed in a groove 19.

A plurality of upper selection lines USL disposed at the same level maybe disposed over the word line WL3 in one stack structure. A separationinsulating layer GSP may be disposed between the upper selection linesUSL. The cell strings coupled to the active pillars AP sharing the bitline BL may be separated from each other by the separation insulatinglayer GSP.

The active pillar AP may include a first portion being in contact withthe first gate dielectric layer 11 and a second portion spaced apartfrom the first gate dielectric layer 11, and the first portion of theactive pillar AP may include a semiconductor material of which a chargemobility is greater than a charge mobility of silicon. In someembodiments, the active pillar AP may include a first semiconductorlayer 13, a second semiconductor layer 14, and a third semiconductorlayer 15. The first semiconductor layer 13 may be an ‘L’-shaped spacer.The second semiconductor layer 14 may be an T-shaped spacer. The firstand second semiconductor layers 13 and 14 may be spaced apart from thesubstrate 1 by the first gate dielectric layer 11. The firstsemiconductor layer 13 may correspond to the first portion of the activepillar AP, and the second semiconductor layer 14 may correspond to thesecond portion of the active pillar AP. In other words, the mobility ofcarries flowing through the first semiconductor layer 13 may be greaterthat of carriers flowing through silicon. For example, the firstsemiconductor layer 13 may be formed of at least one of germanium (Ge),silicon-germanium (SiGe), gallium-arsenic (GaAs), indium-gallium-arsenic(InGaAs), and/or aluminum-gallium-arsenic (AlGaAs). In some embodiments,a germanium content may be higher than a silicon content in thesilicon-germanium (SiGe) of the first semiconductor layer 13. The firstsemiconductor layer 13 may have a thickness or a width of about 50 Å orgreater.

The second semiconductor layer 14 may be formed of a semiconductor layerof which a silicon content is higher than that of the first portion(e.g., the first semiconductor layer 13) of the active pillar AP. Forexample, the second semiconductor layer 14 may be formed of a siliconlayer. However, the inventive concept is not limited thereto. In someembodiments, the second semiconductor layer 14 may be formed of asilicon-germanium (SiGe) layer having a high silicon content or asilicon carbide layer (SiC). The third semiconductor layer 15 may be incontact with the substrate 1. The third semiconductor layer 15 may be asilicon layer, a silicon-germanium (SiGe) layer having a high siliconcontent, or a silicon carbide layer. In some embodiments, the firstsemiconductor layer 13 may include a first silicon-germanium (SiGe)layer having a high germanium (Ge) content, the second semiconductorlayer 14 may include a second silicon-germanium (SiGe) layer having alow germanium (Ge) content, and the third semiconductor layer 15 mayinclude a silicon layer. In other words, the germanium content of thefirst silicon-germanium (SiGe) layer may be higher than the germaniumcontent of the second silicon-germanium (SiGe) layer. For example, thefirst semiconductor layer 13 may include a first silicon-germanium(SiGe) layer having a germanium content of about 50% or greater, and thesecond semiconductor layer 14 may include a second silicon-germanium(SiGe) layer having a germanium content lower than 50%. In other words,the first semiconductor layer 13 may include a first silicon-germanium(SiGe) layer having a silicon content lower than 50%, and the secondsemiconductor layer 14 may include a second silicon-germanium (SiGe)layer having a silicon content of 50% or greater.

The active pillar AP may have an amorphous structure, a poly-crystallinestructure, or a single-crystalline structure. In other words, the firstto third semiconductor layers 13, 14, and 15 may be in the amorphousstate, the poly-crystalline state, or the single-crystalline state. Thefirst to third semiconductor layers 13, 14, and 15 may not be doped withdopants. In some embodiments, the first to third semiconductor layers13, 14, and 15 may be doped with dopants of which a conductivity type isopposite to that of dopants doped in the common source line CSL. In someembodiments, the second semiconductor layer 14 may be omitted, and thethird semiconductor layer 15 may be in direct contact with the firstsemiconductor layer 13.

When the semiconductor memory device according to some embodiments isdriven, voltages may be applied to the gate electrodes to generatechannels in the channel regions defined in a portion (i.e., the firstsemiconductor layer 13) of the active pillar AP adjacent to the firstgate dielectric layer 11.

The charge mobility according to a material is represented in thefollowing table 1.

TABLE 1 Gallium- Silicon (Si) Germanium (Ge) arsenic (GaAs) Electronmobility 1500 3900 8500 (cm²/V-sec) Hole mobility 450 1900 400(cm²/V-sec)

Referring to the Table 1, the electron mobility of the germanium and theelectron mobility of the gallium-arsenic are greater than that of thesilicon. Since the portion used as the channel region is formed of thesemiconductor layer having the excellent charge mobility, a cell currentof the semiconductor memory device may increase.

Source/drain regions corresponding to an inversion layer may begenerated in the first semiconductor layer 13 by a fringe field causedby the voltages applied to the gate electrodes. The channel region isdefined between the source/drain regions. At this time, a thickness ofthe inversion layer may vary with the voltages applied to the gateelectrodes. However, the thickness of the inversion layer may be about50 Å or greater. Since the thickness of the first semiconductor layer 13may be equal to or greater than the thickness of inversion layer, thecharge mobility of an entire portion of the channel region may beimproved. In other words, the thickness of the first semiconductor layer13 may be about 50 Å or greater.

Now will be described a method of fabricating the semiconductor memorydevice.

FIGS. 4 to 9 are cross-sectional views illustrating a method offabricating the semiconductor memory device of FIG. 3.

Referring to FIG. 4, a buffer oxide layer 3 may be formed on a substrate1. Sacrificial layers 5 and intergate insulating layers 7 may bealternately stacked on the buffer oxide layer. The sacrificial layers 5are formed of a material having an etch selectivity with respect to theintergate insulating layers 7. For example, the intergate insulatinglayer 7 may be formed of a silicon oxide layer. The sacrificial layer 5may be formed of a silicon nitride layer, a poly-silicon layer, or asilicon-germanium layer.

Referring to FIG. 5, the intergate insulating layers 7, the sacrificiallayers 5, and the buffer oxide layer 3 may be successively patterned toform active holes 9 exposing the substrate 1.

Referring to FIG. 6, a first gate dielectric layer 11, a firstsemiconductor layer 13, and a second semiconductor layer 14 may beconformally formed on the substrate 1 having the active holes 9 in theorder named. The first gate dielectric layer 11, the first semiconductorlayer 13, and the second semiconductor layer 14 may be sequentiallystaked on a sidewall of the active hole 9. Subsequently, the secondsemiconductor layer 14, the first semiconductor layer 13, and the firstgate dielectric layer 11 may be anisotropically etched until thesubstrate 1 is exposed. Thus, the first gate dielectric layer 11, thefirst semiconductor layer 13, and the second semiconductor layer 14 maybe formed to have spacer shapes. In some embodiments, the first gatedielectric layer 11 may be formed of a triple layer including a siliconoxide layer, a silicon nitride layer, and a silicon oxide layer. Thefirst semiconductor layer 13 may be formed of a material of which chargemobility is greater than that of silicon. For example, the firstsemiconductor layer 13 may be formed of at least one of germanium (Ge),silicon-germanium (SiGe), gallium-arsenic (GaAs), indium-gallium-arsenic(InGaAs), and/or aluminum-gallium-arsenic (AlGaAs). In some embodiments,the germanium content may be higher than the silicon content in thesilicon-germanium (SiGe) of the first semiconductor layer 13. The secondsemiconductor layer 14 may be formed of a semiconductor layer of which asilicon content is higher than that of the first semiconductor layer 13.For example, the second semiconductor layer 14 may be formed of asilicon layer. However, the inventive concept is not limited thereto. Insome embodiments, the second semiconductor layer 14 may be formed of asilicon-germanium (SiGe) layer having a silicon content higher than agermanium content, or a silicon carbide layer (SiC). In someembodiments, the first semiconductor layer 13 may include a firstsilicon-germanium (SiGe) layer having a high germanium (Ge) content, andthe second semiconductor layer 14 may include a second silicon-germanium(SiGe) layer having a low germanium (Ge) content. In other words, thegermanium content of the first silicon-germanium (SiGe) layer may behigher than the germanium content of the second silicon-germanium (SiGe)layer. For example, the first semiconductor layer 13 may include a firstsilicon-germanium (SiGe) layer having a germanium content of 50% orgreater, and the second semiconductor layer 14 may include a secondsilicon-germanium (SiGe) layer having a germanium content lower than50%. In other words, the first semiconductor layer 13 may include afirst silicon-germanium (SiGe) layer having a silicon content lower than50%, and the second semiconductor layer 14 may include a secondsilicon-germanium (SiGe) layer having a silicon content of about 50% orgreater.

While the first and second semiconductor layers 13 and 14 are formed,the first and second semiconductor layers 13 and 14 may be formed tohave a poly-crystalline structure by a solid phase crystallizationmethod.

Referring to FIG. 7, a third semiconductor layer 15 may be conformallyformed on the substrate 1, and then, a first filling layer 17 may beformed to fill each of the active holes 9. The third semiconductor layer15 may be a silicon layer. However, the inventive concept is not limitedthereto. In some embodiments, the third semiconductor layer 15 may beformed of a silicon-germanium (SiGe) layer having a high siliconcontent, or a silicon carbide layer. In some embodiments, the secondsemiconductor layer 14 may not be formed, and the third semiconductorlayer 15 may be formed to be in direct contact with the firstsemiconductor layer 13. A planarization process may be performed on thefirst filling insulation layer and the third semiconductor layer 15. Asa result, the first gate dielectric layer 11, an active pillar AP, and afirst filling insulation pattern 17 may be formed in each of the activeholes 9. When the third semiconductor layer 15 is formed, the thirdsemiconductor layer 15 may be formed to have a poly-crystallinestructure by a solid phase crystallization method. However, theinventive concept is not limited thereto. The third semiconductor layer15 may be formed to have a single-crystalline structure. In someembodiments, the crystal structures of the first and secondsemiconductor layers 13 and 14 may be converted into asingle-crystalline structure during the formation of the thirdsemiconductor layer 15.

Referring to FIG. 8, the intergate insulating layers 7, the sacrificiallayers 5, and the buffer oxide layer 3 may be successively patterned atpositions spaced apart from the active holes 9 to form grooves 19exposing the substrate 1. An ion implantation process may be performedto form a common source line CSL in the substrate 1 under each of thegrooves 19 and a drain region D in a top end portion of the activepillar AP.

Referring to FIGS. 2 and 9, an isotropic etching process may beperformed to remove the sacrificial layers 5 through the grooves 19.Thus, empty regions 19 a are formed between the intergate insulatinglayers 7.

Referring again to FIGS. 2 and 3, a second gate dielectric layer 22 maybe conformally formed in the empty regions 19 a. Subsequently, aconductive layer may be formed to fill the empty regions 19 a and atleast a portion of the groove 19 by a deposition process. The conductivelayer disposed in the groove 19 may be removed to form lower selectionlines LSL, word lines WL0 to WL3, and upper selection lines USL. Asecond filling insulation pattern 20 may be formed to fill the groove19. Thereafter, a separation groove 21 may be formed to divide the upperselection lines USL into upper selection line segments laterallyseparated from each other, and a separation insulating layer GSP may beformed to fill the separation groove 21. Next, a bit line BL may beformed to be connected to the drain region D.

In the method of fabricating the semiconductor memory device describedabove, a portion of the active pillar AP in which a channel region isnot defined may be formed of the silicon layer. Thus, semiconductorfabricating processes skilled in processing the silicon layer may bedirectly applied to the fabricating method of the semiconductor memorydevice according to some embodiments of the inventive concept. Thismeans that the semiconductor memory device may be easily fabricated.

FIG. 10 is a cross-sectional view taken along a line A-A° of FIG. 2 toillustrate a semiconductor memory device according to some embodimentsof the inventive concept.

Referring to FIG. 10, in a semiconductor memory device according to someembodiments, a sidewall of each of the active holes 9 is not coveredwith the gate dielectric layer. An active pillar AP may include a firstsemiconductor layer 13 and a second semiconductor layer 14. The firstsemiconductor layer 13 may be formed of a material of which chargemobility is greater than that of silicon. For example, the firstsemiconductor layer 13 may be formed of at least one of germanium (Ge),silicon-germanium (SiGe), gallium-arsenic (GaAs), indium-gallium-arsenic(InGaAs), and/or aluminum-gallium-arsenic (AlGaAs). The firstsemiconductor layer 13 may have a thickness or a width of about 50 Å orgreater than 50 Å. The second semiconductor layer 14 may include apoly-silicon layer. The first semiconductor layer 13 may be in contactwith the substrate 1. The first semiconductor layer 13 and the secondsemiconductor layer 14 may have cup shapes instead of spacer shapes. Agate dielectric layer 11 may be disposed between the first semiconductorlayer 13 and each of the lines LSL, WL, and USL and between each of thelines LSL, WL, and USL and the intergate insulating layers 7 adjacentthereto. The gate dielectric layer 11 may include a tunnel dielectriclayer, a charge storage layer, and a blocking dielectric layer.

FIG. 11 is a cross-sectional view illustrating a method of fabricatingthe semiconductor memory device of FIG. 10.

Referring to FIG. 11, a first semiconductor layer 13 and a secondsemiconductor layer 14 may be sequentially formed on an entire topsurface of the substrate 1 of the structure illustrated in FIG. 5. Thefirst and second semiconductor layers 13 and 14 may be conformallyformed on the substrate 1. Next, a first filling insulation layer 17 maybe formed to fill each of the active holes 9. A planarization processmay be performed on the first filling insulation layer 17 and the secondand first semiconductor layers 14 and 13 to form an active pillar AP anda first insulation pattern 17 in each of the active holes 9.Subsequently, the processes described with reference to FIGS. 8 and 9may be performed.

FIG. 12 is a cross-sectional view taken along a line A-A′ of FIG. 2 toillustrate a semiconductor memory device according to some embodimentsof the inventive concept. FIG. 13 is an enlarged view of the portion B1of FIG. 12 according to some embodiments of the inventive concept. FIG.14 is a graph illustrating a germanium content according to a positionin an active pillar of FIG. 13.

Referring to FIGS. 12, 13, and 14, an active pillar AP may be formed ofa single-layered silicon-germanium layer according to some embodiments.Here, a germanium content may be varied according to a position in theactive pillar AP. The active pillar AP may include a first portion P1adjacent to the gate dielectric layer 11 and a second portion P2 spacedapart from the first portion P1. In some embodiments, the germaniumcontent of the first portion P1 may be greater than that of the secondportion P2. A silicon content of the first portion P1 may be lower thanthat of the second portion P2. The gate dielectric layer 11 may includea tunnel dielectric layer 11 a, a charge storage layer 11 b, and ablocking insulating layer 11 c. The tunnel dielectric layer 11 a may beformed of a thermal oxide layer, so it may be locally disposed betweenthe active pillar AP and the charge storage layer 11 b.

FIG. 15 is a cross-sectional view illustrating a method of fabricatingthe semiconductor memory device of FIG. 12.

Referring to FIG. 15, a single-layered silicon-germanium layer is formedas an active pillar AP in each of the active holes 9 illustrated in FIG.11 instead of the active pillar AP including the first and secondsemiconductor layers 13 and 14. A difference in the germanium contentmay not occur in the active pillar AP consisting of the single-layeredsilicon-germanium layer when the active pillar AP is formed. However, asidewall of the active pillar AP may be thermally oxidized under anoxygen atmosphere when a gate dielectric layer 11 is formed afterselective removal of the sacrificial layers 5. Reactivity between oxygenand silicon may be greater than reactivity between oxygen and germanium,and thus, the active pillar AP exposed through the empty regions 19 aformed by the removal of the sacrificial layer 5 may be oxidized to beconverted into at least a portion (e.g., the tunnel dielectric layer) ofthe gate dielectric layer 11. Silicon may be consumed in a first portionof the active pillar AP adjacent to the gate dielectric layer 11, so thegermanium content of the first portion of the active pillar AP mayincrease. Since a second portion of the active pillar AP spaced apartfrom the gate dielectric layer 11 may not react with oxygen, thegermanium content of the second portion of the active pillar AP may notincrease. As a result, the germanium content difference according to aposition may occur in the active pillar AP. In addition, the siliconcontent of the first portion of the active pillar AP may be lower thanthat of the second portion of the active pillar AP. Other fabricatingprocesses of the semiconductor memory device may be the same as orsimilar to corresponding ones described with reference to FIGS. 4 to 9.

In some embodiments, the active pillar AP may be formed of thesingle-layered silicon-germanium layer, and a portion of the activepillar AP may be oxidized to form the at least a portion of the gatedielectric layer 11 and to cause a gradient of the germanium contentaccording to the position of the active pillar AP concurrently. Thus,the fabricating processes of the semiconductor memory device may besimplified.

FIG. 16 is a schematic block diagram illustrating an electronic systemincluding a semiconductor device according to some embodiments of theinventive concept.

Referring to FIG. 16, an electronic system 1100 may be used in apersonal digital assistant (PDA), a portable computer, a web tablet, awireless phone, a mobile phone, a digital music player, or otherelectronic products receiving or transmitting information data bywireless.

The electronic system 1100 may include a controller 1110, aninput/output (I/O) unit 1120, a memory device 1130, an interface unit1140, and a data bus 1150. At least two of the controller 1110, the I/Ounit 1120, the memory device 1130, and the interface unit 1140 maycommunicate with each other through the data bus 1150.

The controller 1110 may include at least one of a microprocessor, adigital signal processor, a microcontroller, or other logic devices.Functions of the other logic devices may be a similar to those of themicroprocessor, the digital signal processor and the microcontroller.The memory device 1130 may store commands that are to be executed by thecontroller 1110. The I/O unit 1120 may receive data or signals from anexternal system or may output data or signals to the external system.For example, the I/O unit 1120 may include a keypad, a keyboard and/or adisplay device.

The memory device 1130 may include at least one of the non-volatilememory devices according to some embodiments of the inventive concept.The memory device 1130 may further include at least one of another typeof semiconductor memory devices and volatile random access memorydevices.

The interface unit 1140 may transmit electrical data to a communicationnetwork or may receive electrical data from a communication network.

FIG. 17 is a schematic block diagram illustrating a data storage deviceincluding a semiconductor memory device according to some embodiments ofthe inventive concept.

Referring to FIG. 17, a data storage device 1200 for storinghigh-capacity data may include a flash memory device 1210 implementedwith at least one of the semiconductor memory devices according to someembodiments of the inventive concept. The data storage device 1200 mayfurther include a memory controller 1220 that controls datacommunication between a host and the flash memory device 1210.

A static random access memory (SRAM) device 1221 may be used as aworking memory of a central processing unit (CPU) 1222. A host interfaceunit 1223 may be configured to include a data communication protocolbetween the data storage device 1200 and the host. An error check andcorrection (ECC) block 1224 may detect and correct errors of data whichare read out from the flash memory device 1210. A memory interface unit1225 may connect the memory controller 1220 to the flash memory device1210 according to some embodiments of the inventive concept. The CPU1222 may control overall operations of the memory controller 1220 forexchanging data. The data storage device 1200 may further include a readonly memory (ROM) storing code data for interfacing with the host.

The semiconductor memory devices and the data storage device describedabove may be encapsulated using various packaging techniques. Forexample, the semiconductor memory devices or the data storage deviceaccording to some embodiments of the present inventive concept may beencapsulated using any one of a package on package (POP) technique, aball grid arrays (BGAs) technique, a chip scale packages (CSPs)technique, a plastic leaded chip carrier (PLCC) technique, a plasticdual in-line package (PDIP) technique, a die in waffle pack technique, adie in wafer form technique, a chip on board (COB) technique, a ceramicdual in-line package (CERDIP) technique, a plastic metric quad flatpackage (PMQFP) technique, a plastic quad flat package (PQFP) technique,a small outline package (SOP) technique, a shrink small outline package(SSOP) technique, a thin small outline package (TSOP) technique, a thinquad flat package (TQFP) technique, a system in package (SIP) technique,a multi-chip package (MCP) technique, a wafer-level fabricated package(WFP) technique and/or a wafer-level processed stack package (WSP)technique.

According to some embodiments of the inventive concept, the firstportion, which is in contact with the gate dielectric layer, of theactive pillar may include the semiconductor material of which the chargemobility is greater than that of silicon. When the semiconductor memorydevice is operated, the channel may be formed in the channel regiondefined in the first portion of the active pillar. Thus, mobility ofcharges in the channel region may increase to increase the cell current.In other words, a cell data read error may be reduced or possiblyprevented by the increased cell current.

In addition, the second portion, in which the channel may not be formed,of the active pillar may include the silicon layer or the semiconductorlayer having the high silicon content. Thus, semiconductor fabricatingprocesses skilled in processing the silicon layer may be directlyapplied to easily fabricate the semiconductor memory device.

According to some embodiments of the inventive concept, the activepillar may be formed of the single-layered silicon-germanium layer, anda portion of the active pillar may be oxidized to form the gatedielectric layer and to cause the gradient of the germanium content ofthe active pillar concurrently. Thus, fabricating processes of thesemiconductor memory device may be simplified.

The above-disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover all suchmodifications, enhancements, and other embodiments, which fall withinthe true spirit and scope of the inventive concept. Thus, to the maximumextent allowed by law, the scope is to be determined by the broadestpermissible interpretation of the following claims and theirequivalents, and shall not be restricted or limited by the foregoingdetailed description.

What is claimed is:
 1. A semiconductor memory device comprising: anactive pillar protruding from a substrate; a gate electrode adjacent toa sidewall of the active pillar; and a gate dielectric layer disposedbetween the active pillar and the gate electrode, wherein the activepillar comprises a first portion that is in contact with the gatedielectric layer and a second portion that is spaced apart from the gatedielectric layer, and wherein the first portion includes a semiconductormaterial having a charge mobility that is greater than a charge mobilityof silicon.
 2. The semiconductor memory device of claim 1, wherein asilicon content of the second portion is higher than a silicon contentof the first portion.
 3. The semiconductor memory device of claim 2,wherein the first portion of the active pillar comprises a firstsemiconductor layer, wherein the second portion of the active pillarcomprises a second semiconductor layer, wherein the first semiconductorlayer includes germanium (Ge), silicon-germanium (SiGe), gallium-arsenic(GaAs), indium-gallium-arsenic (InGaAs), and/or aluminum-gallium-arsenic(AlGaAs), and wherein a silicon content of the second semiconductorlayer is higher than a silicon content of the first semiconductor layer.4. The semiconductor memory device of claim 3, wherein the active pillarfurther comprises a third semiconductor layer covering a sidewall of thesecond semiconductor layer, and wherein the third semiconductor layerincludes a silicon layer.
 5. The semiconductor memory device of claim 1,wherein the active pillar includes a single-layered silicon-germaniumlayer, and wherein a germanium content of the first portion is higherthan a germanium content of the second portion.
 6. The semiconductormemory device of claim 5, further comprising: a plurality of intergateinsulating layers adjacent to the sidewall of the active pillar anddisposed on and under the gate electrode, wherein the gate dielectriclayer comprises a tunnel dielectric layer, a charge storage layer, and ablocking dielectric layer that are sequentially stacked on the sidewallof the active pillar, wherein the tunnel dielectric layer includes athermal oxide layer and covers only a portion of the sidewall of theactive pillar, and wherein the charge storage layer and the blockingdielectric layer are disposed between the gate electrode and the activepillar and between the gate electrode and one of the plurality ofintergate insulating layers.
 7. The semiconductor memory device of claim1, wherein the gate dielectric layer comprises a tunnel dielectriclayer, a charge storage layer, and a blocking dielectric layer that aresequentially stacked on the sidewall of the active pillar.
 8. Thesemiconductor memory device of claim 1, wherein the first portion has athickness about 50 Å or greater than 50 Å.
 9. The semiconductor memorydevice of claim 1, wherein the active pillar has an amorphous structure,a single-crystalline structure, or a poly-crystalline structure.
 10. Thesemiconductor memory device of claim 1, further comprising: a pluralityof intergate insulating layers adjacent to the sidewall of the activepillar and disposed on and under the gate electrode, wherein the gatedielectric layer extends between the active pillar and the plurality ofintergate insulating layers.
 11. The semiconductor memory device ofclaim 1, wherein the first portion of the active pillar comprises an ‘L’shaped semiconductor layer.
 12. A semiconductor memory devicecomprising: a plurality of intergate insulating layers and a pluralityof gate electrodes alternately stacked on a substrate; an active pillarextending through the plurality of intergate insulating layers and theplurality of gate electrodes and being connected to the substrate; and afirst gate dielectric layer covering a sidewall of the active pillar,wherein the active pillar comprises a first portion that is in contactwith the first gate dielectric layer and a second portion that is spacedapart from the first gate dielectric layer, wherein the first portionincludes a first semiconductor material having a charge mobility that isgreater than a charge mobility of silicon, and wherein the secondportion includes a second semiconductor material having a siliconcontent that is higher than a silicon content of the first semiconductormaterial and being connected to the substrate.
 13. The semiconductormemory device of claim 12, wherein the first gate dielectric layercomprises a tunnel dielectric layer, a charge storage layer, and ablocking dielectric layer which are sequentially stacked on a sidewallof the first portion of the active pillar.
 14. The semiconductor memorydevice of claim 12, wherein the first portion of the active pillarcomprises a first semiconductor layer, wherein the second portion of theactive pillar comprises a second semiconductor layer, wherein the firstsemiconductor layer includes the first semiconductor material, wherein abottom surface of the first semiconductor layer is spaced apart from thesubstrate, and wherein the second semiconductor layer includes a siliconlayer and is connected to the substrate.
 15. The semiconductor memorydevice of claim 14, further comprising: a second gate dielectric layerdisposed between one of the plurality of gate electrodes and one of theplurality of intergate insulating layers and between the first gatedielectric layer and the plurality of gate electrodes, wherein adielectric constant of the second gate dielectric layer is higher than adielectric constant of a silicon oxide layer.
 16. The semiconductormemory device of claim 14, wherein the first semiconductor layerincludes germanium (Ge), silicon-germanium (SiGe), gallium-arsenic(GaAs), indium-gallium-arsenic (InGaAs), and/or aluminum-gallium-arsenic(AlGaAs).
 17. The semiconductor memory device of claim 16, wherein thefirst semiconductor layer of the active pillar has a poly-crystallinestructure.
 18. A semiconductor memory device comprising: an activepillar protruding from a substrate; a plurality of gate electrodessurrounding the active pillar and sequentially stacked on the substrate;and a gate dielectric layer disposed between the active pillar and theplurality of gate electrodes, wherein the active pillar comprises afirst portion that is in contact with the gate dielectric layer and asecond portion that is spaced apart from the gate dielectric layer,wherein the first portion comprises a first semiconductor layer having acharge mobility that is greater a charge mobility of silicon, whereinthe first semiconductor layer has a ‘L’ shape, and wherein the secondportion comprises a second semiconductor layer having a silicon.
 19. Thesemiconductor memory device of claim 18, wherein the first semiconductorlayer includes germanium (Ge), silicon-germanium (SiGe), gallium-arsenic(GaAs), indium-gallium-arsenic (InGaAs), and/or aluminum-gallium-arsenic(AlGaAs), and wherein the second semiconductor layer includes a siliconlayer.
 20. The semiconductor memory device of claim 18, wherein thefirst portion of the active pillar includes a first silicon-germanium(SiGe) layer, wherein the second portion of the active pillar includes asecond silicon-germanium (SiGe) layer, and wherein a silicon content ofthe first silicon-germanium (SiGe) layer is lower than a silicon contentof the second silicon-germanium (SiGe) layer.